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SmGen

License: Free ‎File size: N/A
‎Users Rating: 3.0/5 - ‎1 ‎votes

ABOUT SmGen

SmGen is a finite state machine generator for Verilog. Not an FSM entry tool though. The input is behavioral-like Verilog. SmGen generates a synthesizabe FSM based design from it. Clock boundaries are explicitly provided by the designer.

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