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Logic Circuit Simulation in C++ 0.0.59

License: Free ‎File size: N/A
‎Users Rating: 5.0/5 - ‎2 ‎votes

ABOUT Logic Circuit Simulation in C++

libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.

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