equ-iitg formal equivalence checker 1.2

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This is a formal equivalence checking tool developed @ IIT Guwahati which can be used to verify functional equivalence between circuits (combinational and sequential) of the formats BLIF, verilog and EDIF.

VERSION HISTORY

  • Version equiitg_1.2%20beta posted on 2009-07-02
    Several fixes and updates
  • Version equiitg_1.2 beta posted on 2009-07-02

Program Details