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sim-sim

License: Free ‎File size: N/A
‎Users Rating: 4.1/5 - ‎7 ‎votes
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HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL

VERSION HISTORY

  • Version releases posted on 2011-02-18
    Several fixes and updates
  • Version N/A posted on 2011-02-18

Program Details

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